/*
 * All Rights Reserved (C) 2021-2025
 * Exoligent SARL (Colombes, France)
 * Website: www.exoligent.com
 * Author : Maxime Coroyer <maxime.coroyer@exoligent.com>
 */

#ifndef __POWERFIP_MBOX_COMMON_H
#define __POWERFIP_MBOX_COMMON_H

/**
 * PowerFIP mailboxes characteristics (specialization)
 */
#define PWRFIP_MBOX_COUNT 3
#define PWRFIP_MBOX_REQ 0 /* async request from host */
#define PWRFIP_MBOX_REP 1 /* async response to host */
#define PWRFIP_MBOX_EVT 2 /* sync event to host */

#define PWRFIP_MBOX_TMO_MS 500 /* default mailbox timeout (500ms) */
#define PWRFIP_MBOX_TMO_TICKS ((PWRFIP_MBOX_TMO_MS) * 100000) /* 10ns ticks */

#define MBOX_AREA_PCI_OFFSET 0x1000u /* MBOXES start offset on PCI BAR1 */
#define MBOX_AREA_APB_OFFSET 0x1000u /* MBOXES start offset on APB */
#define MBOX_WSZ 0x400u /* 1024 32-bit words (=4096B) */
#include "mbox-common.h"

enum pwrfip_mbox_irq_flags {
    /**
     * The first 8 bits are reserved
     * for soft flags of inbox_evt (i.e rdy_code) [mbox[2]]
     */
    PWRFIP_MBOX_IRQ_FIP_ASYNC = (1u << 0), /* fip async. event */
    PWRFIP_MBOX_IRQ_FIP_SYNC = (1u << 1), /* fip sync. event (synchro var) */
    /**
     * Mboxes ack/rdy it flags
     */
    PWRFIP_MBOX_IRQ_EVT_RDY = (1u << 29), /* mbox[2]: it on inbox rdy signal */
    PWRFIP_MBOX_IRQ_REP_RDY = (1u << 30), /* mbox[1]: it on inbox rdy signal */
    PWRFIP_MBOX_IRQ_REQ_ACK = (1u << 31), /* mbox[0]: it on outbox ack signal */
};

/**
 * GCTL register
 */
/** MASK & SHIFT **/
/* reset cpu */
#define CPU_RST_MASK        0x01u
#define CPU_RST_SHIFT       0u
/* general reset (cpu + logic) */
#define ALL_RST_MASK        0x01u
#define ALL_RST_SHIFT       1u
/* enable/disable pci global interrupts (legacy) */
#define INT_LEG_ENA_MASK    0x01u
#define INT_LEG_ENA_SHIFT   16u
/* enable/disable pci separated interrupts (msi) */
#define INT_MSI_ENA_MASK    0x01u
#define INT_MSI_ENA_SHIFT   17u
/** COMMANDS **/
enum pwrfip_gctl_cmd {
    CPU_RST = ((1u & (CPU_RST_MASK)) << (CPU_RST_SHIFT)),
    ALL_RST = ((1u & (ALL_RST_MASK)) << (ALL_RST_SHIFT)),
    INT_LEG_ENA = ((1u & (INT_LEG_ENA_MASK)) << (INT_LEG_ENA_SHIFT)),
    INT_MSI_ENA = ((1u & (INT_MSI_ENA_MASK)) << (INT_MSI_ENA_SHIFT)),
};

#endif /* __POWERFIP_MBOX_COMMON_H */
