Compatible cible : FPGA

Functions FIP : master/slave, messaging

Conception : recent project

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1 - Description

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The IP Core (Intellectual Property) dedicated to FIP, allows the use of FIP functionalities in an FPGA, IP-Core FIP integrates the functionalities of PowerFIP (or FullFIP2) :

Bus arbiter
Passive station
Messaging (periodic, aperiodic)

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IP-CORE FIP was developed to allow customers to simplify and master the integration of FIP functionalities in the design / manufacture of their own electronic cards or design. The customer controls the manufacture of his electronic cards / systems.

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2- Customer integration

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Technically, the principle consists of integrating the "PowerFIP controller block" into a development/customer project. The target of the IP module is the MicroSemi brand component. Block management is done through Microsemi Libero software tools. Exoligent provides the .CXZ block file, the customer integrates it into his project, he himself carries out the development of his electronic card with the FIP functionalities. The "PowerFIP controller" key is done via the pre-programmed crypto component ATECC608B (Microchip), pad UDFN.

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3 - Quotation and development
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For a quotation, quantity discount, or a specific development fill the form below

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IP-CORE IP MODULE FIP

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